While RISC OS may now be regarded as a small, niche operating system, with only a tiny fraction of the number of users that more mainstream platforms attract, it does still have a surprisingly vibrant community – so with that in mind, every once in a while I look through a selection of news groups, mailing lists, and forums, looking for announcements that haven’t found their way to me via the RISCOSitory news inbox, and from those compile a ‘snippets’ post. Here, then, is the latest selection of news items…
Read MoreTag: Aemulor
Snippets – 31st December, 2019
With 2019 drawing to a close at the end of today, to be immediately followed by a year with the official designation of 2020, it’s time to round up a selection of news that hasn’t been covered on RISCOSitory over the course of the year.
Read MoreHigh vector builds of Aemulor now available
A couple of years ago, RISC OS Open Ltd started building versions of RISC OS with “zero page relocation” – with the memory map changed such that the kernel’s workspace that started at the bottom of the addressable memory was moved to a higher location. This was an important step for security and stability, and for the future of the operating system. However, it wasn’t ever going to happen without some casualties along the way; software that in some way tried to use or access certain information held in that…
Read MoreARMX6 OS Update 4 and Super Pack 4 released, plus updated Aemulor
Announcement from Andrew Rawnsley, 20th October, 2015. R-Comp Interactive is pleased to announce the release of two major (free) updates for ARMX6 users. These updates are available to download now, and will be included on all new ARMX6 machines as standard.
Read MoreAemulor arrives on BeagleBoard and PandaBoard
Make your 32-bit computer do an Impression (ho-ho) of a 26-bit one! When Castle Technology Ltd launched the IYONIX pc, back in 2002, there was a significant question users needed an answer to before upgrading to the new computer: Would their old software run on the new hardware? The problem was that for all the previous RISC OS computers, the ARM CPUs worked in (or supported in the case of StrongARM) an addressing mode we refer to as ’26-bit’, in which the program counter and processor status flags are contained…
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