Andrew Rawnsley, wearing his RISC OS Developments hat, will be the guest speaker at the next Wakefield RISC OS Computer Club (WROCC) meeting, which takes place on Wednesday, 2nd September, and he will be talking on the subject of 64-bit.
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The next Wakefield RISC OS Computer Club (WROCC) meeting will take place on Wednesday, 4th June, and the guest speaker will be Steve Revill from RISC OS Open Ltd (ROOL).
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The day before the RISC OS North show last week, RISC OS Open Ltd (ROOL) published an announcement in the news section of their website, and emailed a press release to draw attention to it1. Titled ‘“Moonshots” initiative to Secure the Future of the OS’, the announcement outlines a significant problem that the operating system faces – one that most RISC OS users will already be well aware of: That RISC OS is 32-bit, while more and more new Arm processors are 64-bit.
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In the RISC OS world, we (should) all know that RISC OS runs on ARM processors in either 26 or 32-bit mode, depending what hardware (or emulator) you are running it on – and that we are now at the stage where 64-bit only ARM processors are becoming the norm, and RISC OS is unable to run on them.
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